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Dr. Anu Gupta,
Associate Professor
Birla Institute of Technology and Science (BITS Pilani)
Pilani (Rajasthan), India
Department of Electrical and Electronics Engineering
Tel (Office): +91-(01596)-245073 Ext.: 463, 233
E-Mail: anug@bits-pilani.ac.in
Presently working as a Associate Professor in the Electrical and Electronics Engineering department of BITS, Pilani. I hold a post graduate degree in Physics from Delhi University, which I followed up with M.E in Microelectronics from BITS, Pilani. In March 2003, I obtained my PhD from BITS, Pilani, Rajasthan. Please click here for thesis synopsis.
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Research Area
Research interests include-
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Low power Mixed Signal VLSI Design
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HDL Synthesis and FPGA Architectures
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Low Power Analog Circuits Design
EEE C443 Analog and Digital VLSI Design
EEE C424 Microelectronic Circuits
INSTR C313 Microelectronic Circuits
MEL G641 Analog IC Design
MEL G623 Advanced VLSI Design
EEE C381 Electronic Devices and Integrated circuits
EEE C364 Analog Electronics
ES C252 Basic Electronics ( equivalent Electrical Science-I)
ES C231 Circuit Theory ( equivalent Electrical Science-II)
EEE C272 Circuits and Signals
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A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-bit Full Adder Design, Anu Gupta, & Ganesh TS, Journal of Research, IETE, Volume 50, No. 1, Jan.-Feb. 2004
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Performance exploration of adder architectures for small to moderate-sized low power, high performance adders, Anu Gupta, Chandra Shekhar, Journal of Microelectronics International, Vol. 22 No. 3, 2005
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Automation of Clock Distribution Network Design for Digital Integrated Circuits using Divide and Conquer technique, Anu Gupta, Bipin Naraynan Kulkarni, Integration, the VLSI Journal, Vol 39, issue 4, pp 407-419, ELSEVIER, 2006
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On-chip resistors can make a stable current reference, Nikhil Bhattar, Anu Gupta , Potentials, IEEE Publication Date: Jan.-Feb. 2008 Volume: 27, Issue: 1 ISSN: 0278-6648, Digital Object Identifier: 10.1109/MPOT.2007.913680, Posted online: 2008-01-14 14:16:15.0
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Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology, International Journal of Recent Trends in Engineering, Vol. 1, No. 4, May 2009
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A Novel Redundant Binary Number to Natural Binary Number Converter,” S K Sahoo, Anu Gupta, Abhijit Asati, Chandra Shekhar, Journal of VLSI Signal Processing Systems, 2009, DOI 10.1007/s11265-009-0392-x (impact factor 0.779)
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Dual Channel Addition Based FFT Processor Architecture for Signal and Image Processing, Subhendu Kumar Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati and Anu Gupta, Int. J. High Performance Systems Architecture, Vol. 2, No. 1, 2009, pp:35-45.
Talks Delivered In Conferences/ Workshops/ Seminars/ Training Programs/ OTHER COLLEES
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Adder Architectures for fully static and complementary pass logic designs., Anu Gupta, Proceedings of the national seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec. 10-11, 2000
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Clocking Strategies, Anu Gupta, VLSI Workshop, Oct. 10-11, BITS, Pilani , 2002
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Design Exploration of Architecture for Optimal Adder Synthesis, Anu Gupta, IETE Golden Jubilee Seminar on Electronic Design Automation: Issues and Challenges, April 26, 2003
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Sequential Logic Design, Anu Gupta, National Workshop on VLSI Design and Embedded Systems, BITS, Pilani, 24-26 February 2006
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challenges in Analog IC design, Anu Gupta, Workshop on Analog and RF Design (ARFD 2007), 16th – 18th March, 2007, Birla Institute of Technology and Science, Pilani – 333 031, Rajasthan
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Industry Institute Interaction--fostering ideas to product, Convention on University Industry Linkage through Practice School Programme, 8th -10th March 2007, Birla Institute of Technology and Science, Pilani – 333 031, Rajasthan
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Technology Business Incubator at BITS-PILANI , Convention on Energizing Entrepreneurship in Academia through Innovations (2-3 Nov.2007),(2008)
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High performance adder architectures for fast multi operand addition, Anu Gupta, Workshop on High Performance Digital System Design, 16th – 18th January 2009, Birla Institute of Technology and Science, Pilani – 333 031, Rajasthan
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Invited Lectures on Integrated Circuit Design, bits pilani ,goa campus , 3-5 April 2009
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Analog and Digital VLSI Design Research at BITS, Indo -Taiwan Workshop on Nano, Microelectronics & Embedded Systems at , Birla Institute of Technology and Science, Pilani , 24th-25th September 2010
participation in conferences/ workshops/ seminars/ training programs held at bits, pilani
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Short term intensive course on Electronics and Telecommunication, One and a half month Training Program for Police Telecom Officers (sponsored by Deptt. Of Coordination of Police, Ministry of Home Affairs) by BITS, Pilani, 16 Dec. 1998 – 5 Feb. 1999.
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Training program in IC Design, One month Training Program for spic Electronics Limited , Chennai, Trainees (6) by BITS, Pilani, & CEERI , 17 Aug. – 25 Sept. 1998.
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Entrepreneurship program-Tech Bazaar , Convention on Energizing Entrepreneurship in Academia through Innovations (2006, 2007, 2008)
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Entrepreneurship development program , Workshop on Faculty development for Technology Entrepreneurship(23-24 Nov. 2007)
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National Conference on Virtual and Intelligent Instrumentation , 13-14 nov 2009
Please click here for my CV.
under graduate PROJECTS SUPERVISED
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Nucleus Member Of Division/Unit, ----
I am managing technology business incubator for last 4 years. The work includes preparation of TBI documents, interacting with incubates to resolve their problems, managing the financial details and coordinating with senior faculty members regarding TBI operations
I am also the handling TECHNOLOGY innovation centre (tic) projects which are given by external industries to be completed at bits pilani. this requires a lot of interaction with company personnel and students
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As Resource Person For IntensiveTeaching Workshop/Subject Workshops,
I am involved as examining faculty in ITW (intensive teaching workshop)
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M E Student Mentoring,
I am mentoring 2-3 students every semester for Professional Practice Course -1 and Professional Practice Course -2 for past 7 years. I have also been coordinating PP-1 course activities every year in I semester.
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Assisting Conduct of Bitsat (Invigilator/Co-Coordinator/Question Bank Preparation Etc.
I prepared questions for ME (online-qualifying) exam
I have been regularly involved in interview of students seeking admission to ME degree programme since 2004 both semesters.
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Committee Work
I was in the organizing committee of Tech Bazaar event in Convention on Energizing Entrepreneurship in Academia through Innovations (2007-08) , (2008-09) held at bits pilani
I am the coordinator of Microelectronics Group at EEE
I am the professor in charge of EEE association for past ~3 years
I attended the professional meeting with companies visiting BITS, pilani and explained VLSI lab facilities to them.
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Development Of New Degree Programmes,
I have been involved in development team of ME (EMBEDDED SYSTEMS) degree program
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Organization of / Participation in Student/Staff Related Activities
I am an advisor for 3- 4 students for every year since 2006. Task is to guide them in case they feel ay difficulty at BITS PILANI, Also a member of Academic Counseling cell (ACC) for year 2010-11
I have also mentored students during apogee in their projects nearly every year. Also, I was involved in paper evaluation, analog design contest evaluation during APOGEE . I am a registration advisor during registration process in both the semesters
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VLSI Design Lab Activities
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PhD qualifying Examination
I have been regularly involved in setting PhD Qualifying and interview of students seeking admission to Ph.D
degree programme for past 10 years in both semesters.
vlsi Workshops/ seminar/ conferences conducted
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Workshop on VLSI Design, Convenor-Anu Gupta, BITS, Pilani , 10-11 Oct. 2002
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Hdl EDA Tools Training Programme for BITS, Pilani faculty members,Convenor-Anu Gupta, BITS, Pilani , 22 May 2004 ---29 May 2004
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National Workshop on VLSI Design and Embedded Systems (Sponsered by Honeywell technologies, Phillips, Convenor-Anu Gupta, Rajnish Sharma, BITS, Pilani, 24-26 February 2006 NWVDES workshop
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National Workshop on Analog and RF Design , Convenor-Anu Gupta, Rajnish Sharma, BITS, Pilani, 16-18 March 2007 ARFD workshop
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Workshop on Faculty development for Technology Entrepreneurship, Convenor-Prof. Arya Kumar, Anu Gupta, BITS, Pilani,, (23-24 Nov. 2007)
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Workshop on high performance digital system design, Convenor-Anu Gupta, S K Sahoo, BITS, Pilani , 16-18 March 2009
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National Conference On Virtual and Intelligent Instrumentation (NCVII-09)) , Organizing Committee member, BITS, Pilani, 13th to 14th Nov., 2009
Member of the editorial committee or reviewed papers for reputed journals
I am in the editorial review board of Scientific Journals International , IETE technical review, 2006 , 2007 , IEEE potentials, 2007
