Registration OPEN for VDAT-2023

Call for Papers

VLSI Design & Test Symposium (VDAT) promotes research and development in various fields of VLSI Design. VDAT began as a small workshop in the year 1998, and in 2005 it acquired the status of an international symposium. The 27th International Symposium on VLSI Design and Test (VDAT-2023) will be jointly hosted by Birla Institute of Technology & Science (BITS), Pilani, and CSIR - Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani. This symposium aims to bring Industries, Academics, Researchers, Startups, MSMEs, and related practitioners together to exchange their ideas for leveraging in their respective fields. The VLSI Society of India, leading institutes and industries actively support the symposium.


Emerging Chip Architectures for Future: Beyond Moore's Law

Low-Power Integrated Circuits and Devices
  • Low-Power Analog/Digital/Mixed Signal Circuits
  • Low-Voltage Low-Power Sensors Interface
  • Circuit design for Reliability
  • Device Modelling and Simulation
  • MEMS/NEMS/MOEMS Devices, Organic Devices
FPGA-based Design and Embedded Systems
  • Adaptive Computing using Reconfigurable Fabrics
  • Large-Scale Systems and Power Networks
  • Hardware-Software Co-design
  • Reconfigurable and FPGA-based Design
  • Multi-FPGA Systems
Memory, Computing & Processor Design
  • Memory Design
  • STT-RAM, PC-RAM, R-RAM, and Memristors
  • Emerging Memory Technologies
  • Neuromorphic Computing
  • Quantum Computing
System-Level Design
  • Systems-on-Chip (SoC), Lab-on-Chip
  • Mixed-Mode System-on-Chip
  • High-Speed Interconnects, Network-on-Chip
  • Wireless Transceivers, Multimedia Processors
  • Heterogeneous and Homogeneous MPSoCs
VLSI Architectures and System Integration
  • VLSI Processors & Signal Processing Architectures
  • RF Integrated Circuits & Systems
  • Machine Learning Architectures
  • Low-Power IoT Architectures and Systems
  • Compressive Sensing, Wireless Systems
Emerging Integrated Circuits and Systems
  • Artificial Intelligence Accelerators
  • Cognitive Computing Systems
  • Printed & Flexible Electronics
  • Low Power Edge Computing System
  • Analog/Digital/Mixed Signal Circuits
VLSI Testing and Security
  • Hardware Security and VLSI Design Optimization
  • Hardware Attacks, Detection, Threat Modelling
  • Fault Diagnosis and Fault Models
  • DFT and BIST for Digital Designs
CAD for VLSI
  • Design Automation and CAD Tools
  • Design Flows for MPSoCs
  • ML/AI based Design-Flows and EDA
  • Design Automation for DFX

Student Fellowship

VDAT-2023 will provide a limited number of fellowships to Undergraduate and Master's students for attending the symposium. Details may be checked out from the website.

Submission Guidelines

  • Authors are invited to submit original, unpublished research manuscripts on the above topics. Papers should be submitted in pdf format (Portable Document Format) as per the IEEE Conference paper format.
  • The number of pages should not exceed six A4 size pages and paper should be uploaded through easy chair portal.
  • There will be double blind review of the paper. Therefore, do not include ‘authors’ name in submitted paper. A paper with ‘authors’ names will not be considered for review.
  • The paper must include an abstract of about 250 words with maximum of five keywords.
  • Authors of the accepted papers will be informed by email. Information about necessary revisions will be communicated to the corresponding author through email.
  • The author(s) will have to incorporate the suggestions and will have to send the revised camera-ready copy of the paper as per the final submission guidelines within the given time limit.
  • It is mandatory for at least one of the authors to register for publication of the paper in proceedings. For the author presenting more than one papers, it is mandatory to register and present each paper separately.

Get In Touch

BITS Pilani, Pilani Campus, Vidya Vihar, Pilani 333031, Rajasthan, India

vdat2023@pilani.bits-pilani.ac.in

+91-1596 - 2555322

Organized by:

© VDAT-2023. All Rights Reserved. Designed by SDET Unit BITS Pilani, Pilani Rajasthan